The present invention relates to a video Digital-to-Analog Converter (DAC). In particular, the invention relates to a video DAC that uses current mirrors with input/output current controllability to achieve low-power consumption and a low-glitch current steered output.
The function of a DAC is to generate a voltage having a magnitude that corresponds to the value of a digital signal. A variety of DAC designs are known, one of which is a current steering DAC. In a current steering DAC, a current having a magnitude corresponding to the value of a digital signal flows through a resistor to generate a voltage having a magnitude corresponding to the digital signal. FIG. 1 is a schematic of a known example of current steering DAC 100 using a resistor R to convert an output current IOUT into an output voltage VOUT. The output current IOUT is generated by 4 current sources 102, 104, 106, 108, although a fewer or greater number of current sources can be used. Each of the current sources 102, 104, 106 and 108 is selectively enabled by a respective complimentary input signal IN, IN*. Only IN, IN* for the current source 102 is shown for clarity. The DAC 100 is often implemented in a semiconductor integrated circuit without the resistor R. In such a case, the resistor R is separately mounted on a circuit board and connected to the semiconductor integrated circuit as shown in FIG. 1.
The DAC 100 may be either unary or binary. In a unary DAC, the currents generated by all of the current sources are identical. In a binary DAC, the currents generated by the current sources are binary weighted so that the current sources generate respective currents of I, 2I, 4I, 8I, etc. A DAC may also include both types of current sources, which is referred to as a segmented or hybrid DAC.
With further reference to FIG. 1, the DAC 100 includes, in addition to the current sources 102, 104, 106 and 108 and the resistor R, a diode-coupled reference transistor 110 through which a reference current Iref flows. The current source 102 includes a mirror transistor 120 having its source and gate coupled in parallel with a source and gate of the reference transistor 110. As a result, the current through the mirror transistor 120 corresponds to, but is not necessarily equal to, the magnitude of the current through the reference transistor 110. The current flowing through the mirror transistor 120 is steered through either a first switching transistor 122 if IN is high or a second switching transistor 124 if IN is low. If the current is steered through the first switching transistor 122, the current contributes to the current IOUT flowing through the resistor R. Alternatively, if the current is steered through the second switching transistor 124, the current contributes to the current IOUT*.
The remaining current sources 104, 106 and 108 operate in substantially the same manner as the current source 102. More specifically, each current source 104, 106 and 108 includes a respective mirror transistor 130, 140, 150, a respective first switching transistor 132, 142, 152 to steer the current through the IOUT path, thereby contributing to the magnitude of the output voltage VOUT, and a respective second switching transistor 134, 144, 154 to steer the current through the IOUT* path. Thus, each current source 102, 104, 106 and 108 contributes to an increase in the current IOUT, and hence VOUT, if the respective complimentary inputs IN, IN* are active.
The DAC 100 shown in FIG. 1 is a segmented or hybrid DAC since it includes both unary current sources and binary current sources. More specifically, the current sources 106, 108 are unary because the mirror transistors 140, 150 are matched to the reference transistor 110, and the gates of the reference and mirror transistors 110, 140, 150 are all connected together, so that transistors 140, 150 source a current exactly equal to Iref. However, for the DAC to be unary, it is not necessary for the current sourced by each of the mirror transistors 140, 150 to be equal to Iref as long as the currents sourced by the mirror transistors 140, 150 are equal to each other. The DAC 100 may include a lesser or greater number of current sources 102, 104, 106 and 108 than shown in FIG. 1. For example, a unary DAC may include 7 current sources in order to provide a current to signal IOUT that may selectively be any of zero or 1, 2, 3, 4, 5, 6 or 7 times Iref. Thus, a conventional binary-to-decimal encoding circuit (not shown) can generate from a 3 bit binary number, the voltages to apply to the gates of the 7 current sources to form what is sometimes called a thermometer or ladder DAC.
As mentioned above, the DAC 100 is a segmented or hybrid DAC because it includes binary current sources as well as unary current sources. In the DAC 100, the current sources 102, 104 are binary because the mirror transistors 120, 130 are not matched to the reference transistor 110. Instead, each mirror transistor 120, 130 is binary scaled with respect to reference transistor 110 and each other so that transistors 120, 130 source a current that is a predetermined multiple of Iref, and also the current through one of the transistors 120, 130 is binary weighted with respect to the current through the other transistor of transistors 120, 130. For example, if the mirror transistor 120 is scaled so that it sources a current that is one times Iref, then the mirror transistor 130 is scaled so that it sources a current that is two times of Iref. By controlling the control voltages applied to the respective current sources 102, 104, the current contributing to Iout can be selectively controlled to be either zero, one, two or three times Iref. Although, in the DAC 100 shown in FIG. 1, one of the currents supplied by one of binary current sources is equal to Iref, this is not required as long as the currents supplied by the binary current sources are binary weighted. A binary DAC may advantageously include more current sources, in increasing binary scale, to achieve greater bit depth.
The segmented or hybrid DAC shown in FIG. 1 may include a fewer or greater number of current sources. For example, a segmented DAC includes a 5 binary current sources with the most significant bit of the binary DAC scaled to source a current that is 16 times Iref, and 7 unary current sources of the type discussed above with each current source scaled to source a current that is 32 times Iref. With proper control of the control voltages applied to the current stages, such a segmented DAC can operate to convert of an 8 bit byte of digital data into a current IOUT that varies from zero up to 255 times Iref in increments of Iref. The segmented architecture is most frequently used to combine high conversion rate and high resolution. In this architecture the least significant bits steer binary weighted current sources, while the most significant bits are thermometer or ladder encoded and steer a unary current source array.
The DAC 100 shown in FIG. 1 and similar DACs have drawbacks. For example, since any current from a current source that does not contribute to IOUT is essentially wasted, and the power consumption of the DAC 100 can be considerably greater than the power dissipated in the resistor R.
In addition, the DAC 100 and similar DACs are prone to produce a glitch or output spike. For example, at the half-scale transition when the most significant bit (MSB) is turned on (or off) and all the other bits are turned off (or on), a glitch having a maximum amplitude will occur. The glitch is mainly due to the following effects:
1) imperfect synchronization of the control voltages, which causes different current sources 102-108 to turn on or off at different times;
2) channel length modulation of the mirror transistors 120, 130, 140, 150 in the respective current sources 102-108 due to voltage fluctuations, particularly VOUT;
3) charge and discharge of parasitic capacitances associated with the current sources 102-108;
4) feed through of digital control voltages to the output of current sources 102-108; and
5) non-symmetrical operation of the switching transistors in the respective current sources 102-108 that can cause both switching transistors in a current source to be simultaneously on or off for a short period.
A DAC circuit according to the invention includes a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output and an output current mirror having an input coupled to the combined current source output. The output current mirror provides current gain to enable the DAC circuit to provide the required output current magnitude while at the same time, enabling the DAC itself to operate with a smaller reference current into the DAC. The output current mirror advantageously is either a regulated cascode current mirror or a high-swing cascode current mirror to provide improved linearity over the operating range of the DAC circuit.
In another example of the DAC circuit according to the invention, the output current mirror includes an input transistor and at least two output transistors. Each of the output transistors are coupled in series through a respective selection switch (e.g., transistor) before being coupled to the output terminal of the DAC circuit. By providing selection control signals to the selection switches, the current gain of the output current mirror is selectively controllable. An advantage of using an output current mirror as discussed is that glitches and output spikes are reduced as if a low pass filter were applied.
In still another example of the DAC circuit according to the invention, the DAC circuit further includes an input current mirror that receives the reference current, the input current mirror includes an input transistor and at least two output transistors. Each of the output transistors are coupled in series through a respective selection switch (e.g., transistor) before being coupled to a reference input transistor coupled to the current sources of the current steered DAC. By providing selection control signals to the selection switches, the current gain of the input current mirror is selectively controllable to accommodate a range of reference current sources.